Flash memory apparatus and method for generating read voltage thereof
US8711626B2 · kind B2 · utility
16Cited by
1References
22Claims
0Family size
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Key dates
| Filing date | Jul 13, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jun 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory apparatus includes: a cell array including a plurality of main blocks, a code addressable memory (CAM) block, and a security block; a control unit configured to detect a threshold voltage change data of a main block to which a program operation has been performed among the plurality of main blocks, and set a trimming value corresponding to the detected threshold voltage change data; and a read voltage generation unit configured to generate a read voltage according to the set trimming value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.