Predicting performance of an integrated circuit
US8712718B1 · kind B1 · utility
7Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Jul 20, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jul 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.