Semiconductor apparatus
US8713349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.