Transistor with self-aligned channel width
US8716768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Apr 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a transistor including a source and a drain disposed in a substrate and a gate disposed above the substrate. The gate includes a first longitudinal member disposed above the source and the drain and running substantially parallel to a channel of the transistor. The first longitudinal member is disposed over a first junction isolation area. The gate also includes a second longitudinal member disposed above the source and the drain and running substantially parallel to the channel of the transistor. The second longitudinal member is disposed over a second junction isolation region. The gate also includes a cross member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member. The cross member is disposed above and between the source and the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.