Static random-access memory cell array with deep well regions
US8716808B2 · kind B2 · utility
5Cited by
2References
14Claims
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Key dates
| Filing date | Apr 12, 2013 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Apr 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.