Bump structure with barrier layer on post-passivation interconnect
US8716858B2 · kind B2 · utility
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12References
20Claims
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Key dates
| Filing date | Jun 24, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Feb 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.