Integrated circuit including a gate and a metallic connecting line
US8716862B2 · kind B2 · utility
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10References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Apr 15, 2010 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 Å or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.