Method and apparatus pertaining to a ferroelectric random access memory
US8717800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1677
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.