Method and apparatus for leakage suppression in flash memory in response to external commands
US8717813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2011 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.