Semiconductor memory device and method of controlling the same
US8717840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.