Patent · US Active

Frequency selection with selective voltage binning

US8719763B1 · kind B1 · utility

15Cited by

5References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Jeanne P. Bickford · South Burlington, US
Eric A. Foreman · Saint Albans, US
Vladimir Zolotov · Putnam Valley, US

Key dates

Filing date	Jan 4, 2013
Grant date	May 6, 2014
Priority date	—
Expiry date	Jan 4, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Approaches for binning integrated circuits using timing are provided. A method includes performing a statistical timing analysis of a design. The method also includes identifying bin sub-spaces within a process space of the design. The method further includes determining a frequency limit for each said bin sub-space. The method additionally includes closing timing to the frequency limit for each said bin sub-space.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.