Patent · US Active

Delay-locked loop and method for a delay-locked loop generating an application clock

US8723570B2 · kind B2 · utility

2Cited by

1References

8Claims

0Family size

Assignee

Etron Technology, Inc. · TW

Inventors

Feng-Chia Chang
Yu-Chou Ke · Zhuhai, CN
Chi-Wei Yen · Hengshan, TW
Chun Shiah · Hsinchu, TW

Key dates

Filing date	Mar 4, 2013
Grant date	May 13, 2014
Priority date	—
Expiry date	Mar 4, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/0805
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.