Method and apparatus pertaining to a ferroelectric random access memory
US8724367B2 · kind B2 · utility
1Cited by
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7Claims
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Key dates
| Filing date | Sep 23, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.