Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell
US8724374B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Nov 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.