Anuj Grover
24Patents
4h-index
13Co-inventors
56Inventor score
Filing activity: Dec 29, 2011 → Oct 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9305633B2 | SRAM cell and cell layout method | Physics | 22 | Active |
| US8982651B2 | Memory with an assist determination controller and associated methods | Physics | 10 | Active |
| US9177637B1 | Wide voltage range high performance sense amplifier | Physics | 6 | Active |
| US8724374B1 | Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell | Physics | 5 | Active |
| US8654570B2 | Low voltage write time enhanced SRAM cell and circuit extensions | Physics | 3 | Active |
| US11094376B2 | In-memory compute array with integrated bias elements | Electricity | 2 | Active |
| US11474788B2 | Elements for in-memory compute | Physics | 2 | Active |
| US11605424B2 | In-memory compute array with integrated bias elements | Electricity | 1 | Active |
| US11257543B2 | Memory management device, system and method | Physics | 0 | Active |
| US12386506B2 | Tagged memory operated at lower VMIN in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US11836346B2 | Tagged memory operated at lower vmin in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US11823771B2 | Streaming access memory device, system and method | Physics | 0 | Active |
| US11398289B2 | Memory calibration device, system and method | Physics | 0 | Active |
| US10277207B1 | Low voltage, master-slave flip-flop | Physics | 0 | Active |
| US11749343B2 | Memory management device, system and method | Physics | 0 | Active |
| US11360667B2 | Tagged memory operated at lower vmin in error tolerant system | Emerging Cross-Sectional Technologies | 0 | Active |
| US11776650B2 | Memory calibration device, system and method | Physics | 0 | Active |
| US10637447B2 | Low voltage, master-slave flip-flop | Physics | 0 | Active |
| US12292780B2 | Computing system power management device, system and method | Physics | 0 | Active |
| US11798615B2 | High density array, in memory computing | Physics | 0 | Active |
| US11335397B2 | High-density array, in memory computing | Physics | 0 | Active |
| US11726543B2 | Computing system power management device, system and method | Physics | 0 | Active |
| US11829730B2 | Elements for in-memory compute | Physics | 0 | Active |
| US12243584B2 | In-memory compute array with integrated bias elements | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.