SRAM cell having an N-well bias
US8724375B2 · kind B2 · utility
2Cited by
8References
12Claims
0Family size
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Key dates
| Filing date | Feb 4, 2013 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. The method may include adjusting a bias level of the n-wells that contain the bit driver, bit-bar driver, bit passgate, and optional bit-bar passgate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.