Semiconductor memory device
US8724391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2012 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | May 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.