SRAM write assist apparatus
US8724420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2011 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.