Tamper resistant memory protection
US8726042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2008 |
| Grant date | May 13, 2014 |
| Priority date | — |
| Expiry date | Feb 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various mechanisms are disclosed for protecting the security of memory in a computing environment. A security layer can have an encryption layer and a hashing layer that can dynamically encrypt and then dynamically hash sensitive information, as it is being loaded to dynamic memory of a computing device. For example, a memory unit that can correspond to a memory page can be processed by the security layer, and header data, code, and protect-worthy data can be secured, while other non-sensitive data can be left alone. Once such information is secured and stored in dynamic memory, it can be accessed at a later time by a processor and unencrypted and hash checked. Then, it can be loaded back onto the dynamic memory, thereby preventing direct memory access attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.