Small footprint phase change memory cell
US8728859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2010 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Feb 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/063
Abstract
An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.