Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
US8729606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2010 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of first and second PMOS transistors, and first and second NMOS transistors has a respective diffusion terminal with a direct electrical connection to a common node, and has a respective gate electrode defined within any one gate level channel. Each gate level channel is uniquely associated with and defined along one of a number of parallel oriented gate electrode tracks. The first PMOS transistor gate electrode is electrically connected to the second NMOS transistor electrode. The second PMOS transistor gate electrode is electrically connected to the first NMOS transistor gate electrode. The first and second PMOS transistors, and the first and second NMOS transistors together define a cross-coupled transistor configuration having commonly oriented gate electrodes formed from respective rectangular-shaped layout features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.