Seal ring structures with reduced moisture-induced reliability degradation
US8729705B2 · kind B2 · utility
3Cited by
28References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.