Clock generator with integrated phase offset programmability
US8729944B2 · kind B2 · utility
3Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2011 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.