Wide-range glitch-free asynchronous clock switch
US8729947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.