Inventor · Palo Alto, CA, US

Ali Vahidsafa

34Patents
3h-index
38Co-inventors
63Inventor score

Filing activity: Aug 31, 1988 → Jun 9, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US4920485A Method and apparatus for arbitration and serialization in a multiprocessor system Physics 28 Expired
US9026705B2 Interrupt processing unit for preventing interrupt loss Physics 18 Active
US8729947B2 Wide-range glitch-free asynchronous clock switch Electricity 4 Active
US10528351B2 Method for migrating CPU state from an inoperable core to a spare core Emerging Cross-Sectional Technologies 3 Active
US9509317B2 Rotational synchronizer circuit for metastablity resolution Electricity 3 Active
US8726114B1 Testing of SRAMS Physics 3 Active
US8839025B2 Systems and methods for retiring and unretiring cache lines Physics 2 Active
US11263012B2 Method for migrating CPU state from an inoperable core to a spare core Emerging Cross-Sectional Technologies 2 Active
US9218018B2 Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain Physics 2 Active
US9710273B2 Method for migrating CPU state from an inoperable core to a spare core Emerging Cross-Sectional Technologies 2 Active
US9323600B2 Systems and methods for retiring and unretiring cache lines Physics 1 Active
US10467139B2 Fault-tolerant cache coherence over a lossy network Electricity 1 Active
US8943375B2 Combo static flop with full test Physics 1 Active
US10248520B2 High speed functional test vectors in low power test conditions of a digital integrated circuit Physics 1 Active
US9645903B2 Managing failed memory modules Physics 1 Active
US9746876B2 Drift compensation for a real time clock circuit Electricity 1 Active
US8181073B2 SRAM macro test flop Physics 1 Active
US9569322B2 Memory migration in presence of live memory traffic Physics 0 Active
US10452547B2 Fault-tolerant cache coherence over a lossy network Physics 0 Active
US10656205B2 Narrow-parallel scan-based device testing Physics 0 Active
US9355211B2 Unified tool for automatic design constraints generation and verification Physics 0 Active
US9460013B2 Method and system for removal of a cache agent Physics 0 Active
US8972767B2 Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time reference Physics 0 Active
US9404967B2 Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit Physics 0 Active
US11709742B2 Method for migrating CPU state from an inoperable core to a spare core Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.