Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
US8730710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2013 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.