3D non-volatile memory device and method for operating and fabricating the same
US8730727B2 · kind B2 · utility
9Cited by
1References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 19, 2010 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jul 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.