Semiconductor device for accelerating erase verification process and method therefor
US8730739B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.