Patent · US Active

Dual clock edge triggered memory

US8730756B2 · kind B2 · utility

1Cited by

5References

28Claims

0Family size

Assignees

STMicroelectronics International N.V. · NL
STMicroelectronics SA

Inventors

Nishu Kohli · Kunzer, IN
Robin Wilson · Holywood, GB

Key dates

Filing date	Dec 6, 2011
Grant date	May 20, 2014
Priority date	—
Expiry date	Jun 11, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/222
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.