Method and apparatus for protecting, optimizing, and reporting synchronizers
US8732639B1 · kind B1 · utility
5Cited by
1References
37Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 3, 2009 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.