Method for achieving an efficient statistical optimization of integrated circuits
US8732642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Aug 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.