Method and system for hardware enforced virtualization in an integrated circuit
US8732806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2009 |
| Grant date | May 20, 2014 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a method and system for hardware enforced virtualization in an integrated circuit are provided. In this regard, a mode of operation of an integrated circuit may be controlled such that the integrated circuit alternates between a secure mode of operation and an open mode of operation. Various resources of the integrated circuit may be designated as open or secure, and secure resources may be made inaccessible while the integrated circuit operates in the open mode. Access to the secure resources may be controlled based on a configuration of one or more registers and/or switching elements. Resources designated as secure may comprise, for example, a one-time-programmable memory. The integrated circuit may comprise ROM and/or one-time-programmable memory that stores one or more instructions, wherein execution of the one or more instructions may control transitions between the secure mode and the open mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.