Copper etch scheme for copper interconnect structure
US8735278B2 · kind B2 · utility
6Cited by
0References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 17, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.