Semiconductor packaging process using through silicon vias
US8735287B2 · kind B2 · utility
3Cited by
83References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.