Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
US8735944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2010 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features that are each defined within any one gate level channel. At least a portion of the first p-type diffusion region and at least a portion of the second p-type diffusion region are formed over a first common line of extent that extends perpendicular to the first parallel direction. Also, at least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a second common line of extent that extends perpendicular to the first parallel direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.