Non-volatile memory device formed by dual floating gate deposit
US8735959B2 · kind B2 · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Nov 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.