Embedded electronic device package structure
US8736033B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0715
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embedded-electronic-device package includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer, a shielding-metal layer and conductive vias. The core layer includes a first surface, a second surface opposite to the second surface and a cavity penetrating the core layer. The electronic device is disposed in the cavity including an inner surface. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers part of the electronic device. The second dielectric layer disposed on the second surface is filled in rest of the cavity, covers rest of the electronic device. The first and second dielectric layers cover the electronic device. The shielding-metal layer covers the inner surface. The conductive vias are respectively disposed in the first and second dielectric layers and extended respectively from outer surfaces of the first and second dielectric layers to the shielding-metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.