Multi-chip stacking of integrated circuit devices using partial device overlap
US8736076B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.