High precision single edge capture and delay measurement circuit
US8736338B2 · kind B2 · utility
4Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Jul 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains (241, 242) having different delay values connected to sampling latches (222-227) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.