Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory
US8737132B2 · kind B2 · utility
1Cited by
42References
10Claims
0Family size
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Key dates
| Filing date | Aug 9, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Aug 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.