Method for and flash memory device having improved read performance
US8737135B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Mar 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Flash memory device operable under a single-bit or multiple-bit serial protocol is provided with a capability to determine the address boundary condition of an application from the address field of an address boundary configurable (“ABC”) read command. Based on the identified address boundary condition, the Flash memory device may perform multiple sensing of the memory array as required by the ABC read command using optimal internal sense times for each sensing. The number of dummy bytes may be specified for the read command in advance by the user, based on the address boundary of the application and the desired frequency of operation of the Flash memory device. Therefore, Flash memory device read performance is improved both by minimizing the number of dummy bytes in the read command and by optimizing the internal sense times for the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.