Write-leveling system and method
US8737161B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2013 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Feb 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for use with a DRAM, a DQS signal provider, a clock signal provider, a DQS line and a clock line. The DQS line can provide the DQS signal from the DQS signal provider to the DRAM. The clock line can provide the clock signal from the clock signal provider to the DRAM. The system includes a clock delay determining portion, a DQS delay determining portion, and adjustment portion and a controlling portion. The clock delay determining portion can determine a clock delay. The DQS delay determining portion can determine a DQS delay. The adjustment portion can generate an adjustment value based on the clock delay and the DQS delay. The controlling portion can instruct the DQS signal provider to adjust a time of providing a second DQS signal based on the adjustment value, wherein the clock delay is less than the DQS delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.