Mixed concurrent and serial logic simulation of hardware designs
US8738350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.