Memory mapping in a processor having multiple programmable units
US8738886B2 · kind B2 · utility
0Cited by
348References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Sep 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.