Circuit, biasing scheme and fabrication method for diode accessed cross-point resistive memory array
US8741728B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.