Three-dimensional wafer stacking with vertical interconnects
US8741737B2 · kind B2 · utility
4Cited by
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30Claims
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Key dates
| Filing date | Sep 20, 2007 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jan 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.