Methods of manufacturing three-dimensional semiconductor devices
US8741761B2 · kind B2 · utility
25Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2011 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Aug 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.