Through silicon via dies and packages
US8741762B2 · kind B2 · utility
2Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Oct 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.