Three-dimensional semiconductor memory devices and methods of fabricating the same
US8742488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2012 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Feb 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.