Recessed and embedded die coreless package
US8742561B2 · kind B2 · utility
11Cited by
58References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Jun 3, 2014 |
| Priority date | — |
| Expiry date | Jun 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.